On-Package Communication for Heterogeneous 2.5D Chiplet Systems

About the Project

The semiconductor industry is rapidly shifting towards modular design based on chiplets and Multi-Chip Modules, where multiple dies — CPUs, GPUs, AI accelerators, memory stacks — are integrated side by side on a common interposer. This paradigm offers compelling advantages in cost, flexibility, and performance, but introduces a fundamental challenge: the communication fabric connecting heterogeneous chiplets must cope with highly dynamic, workload-dependent traffic while remaining robust against link degradation and partial failures.

This research addresses that challenge through the design of a Smart Network-on-Chip (SNoC): an asynchronous communication chiplet integrating elements of intelligence. The core idea is to embed lightweight inference engines directly into the router microarchitecture, enabling each routing node to autonomously observe local traffic conditions, congestion signals, and link health indicators, and to translate these observations into real-time routing and reconfiguration decisions, without relying on a centralized controller or a global clock.

The research develops along two complementary directions. The first concerns adaptive routing: replacing static routing heuristics with data-driven policies capable of generalizing across diverse workload phases and traffic regimes. The second concerns reliability-aware reconfiguration: exploiting the same distributed observation capability to detect link degradation, anticipate failures, and proactively reconfigure the fabric before faults propagate to the system level. Both directions are grounded in an existing RTL-verified asynchronous NoC IP, which serves as the hardware foundation for the proposed extensions.

We are looking for two motivated PhD candidates with a background in digital design, computer architecture, and/or the backend digital design flow, and an interest in the intersection of hardware design and intelligent systems. Prior experience with RTL design, system architecture simulation, and/or machine learning for hardware is a plus. The research framework outlined above is intentionally broad, and is meant to accommodate a range of specific research directions that candidates may wish to develop based on their own interests, background, and skills. What matters most is intellectual rigor and the ability to identify, within this framework, a consistent and original research idea.

Candidates with an interest in LLM-aided design methodologies and agentic approaches to hardware design space exploration are also encouraged to apply, as these tools are expected to play an increasing role in the research workflow.

Eligibility

Applicants should have, or expect to achieve, at least a 2.1 honours degree or a master’s (or international equivalent) in a relevant science or engineering related discipline.

Funding

This 3.5-year PhD project is fully funded; students who are eligible to pay tuition fees at the Home rate are eligible to apply. The successful candidate will receive an annual tax-free stipend set at the UKRI rate (£21,805 for 2026/27) and tuition fees will be paid. We expect the stipend to increase each year. The start date is October 2026.