Question 1

What qualifications are required for this Research Assistant/Associate in AI Hardware role?

Accepted Answer

Appointment at Research Associate level requires a PhD ; those with submitted PhD will start as Research Assistant and upgrade upon award. Extensive experience with FPGA tools is viable with ASIC/EDA training provided. Focus on hardware design expertise over ML training or novel devices. See research assistant jobs for similar roles or academic CV tips .

Question 2

What key skills and tools are needed for designing next-generation AI Hardware accelerators?

Accepted Answer

Essential: Experience with complex digital hardware designs , EDA tools from Cadence/Synopsys, architectural/microarchitectural optimisations, PPA estimation via ASIC flows. Beneficial: Design verification (DV) , CI setups , knowledge of machine learning workloads and accelerators. FPGA background trainable for ASIC. Explore postdoc research tips .

Question 3

How do I apply for this University of Cambridge AI Hardware position?

Accepted Answer

Click 'Apply' on the jobs.cam.ac.uk portal, register, upload CV and covering letter outlining fit to criteria. Quote reference NR46280 . No extra docs considered. Informal enquiries to Prof. Rob Mullins. Deadline: 6 July 2025 . Use free cover letter template and resume template for preparation.

Question 4

What is the salary, contract duration, and employment type?

Accepted Answer

Salary : £32,546-£45,413. Full-time fixed-term until 30 September 2027, funded by UK's ARIA. UK work eligibility required. Check university salaries for benchmarks.

Question 5

What is the team and collaboration like on this AI Hardware project?

Accepted Answer

Cambridge team: Prof. Robert Mullins (PI), Prof. Timothy Jones, Dr Rika Antonova, 3 PhDs, 1 postdoc. Led by Dr. Yiren Zhao (Imperial), with Profs. George Constantinides/Wayne Luk (Imperial), Dr. Mai Luo/Prof. Michael O'Boyle (Edinburgh). Collaborate with >12 PhDs/postdocs on accelerator design , simulation , optimisation. Part of ARIA's 1000x AI cost reduction program. View faculty jobs for team contexts.

Question 6

Is experience with machine learning accelerators advantageous?

Accepted Answer

Yes, knowledge of ML workloads and ML accelerator design is advantageous but not essential. Priority on hardware design and tools; novel semiconductors or ML training less relevant. Training provided for ASIC from FPGA experience.

Research Assistant/Associate in Design of Next-Generation AI Hardware (Fixed Term)

University of Cambridge

The Old Schools, Trinity Ln, Cambridge CB2 1TN, UK

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Research Assistant/Associate in Design of Next-Generation AI Hardware (Fixed Term)